Prior to the present invention arrangements for displaying raster test patterns involved a relatively large bit-mapped memory, usually addressed by counters generating horizontal and vertical raster timing. For a display memory which is constantly changing this is an acceptable approach. However, for displaying simple test patterns such as, for example, a monochromatic display with two level video, i.e. on and off, much of the memory is wasted in the described prior art arrangement.
Consider, for example, the requirements for a wide field of view head-up display (HUD) as is common for avionics video test equipment. Two display modes are required: 525 lines per frame and 875 lines per frame, both at a 30 Hz refresh rate and 2:1 interlaced. In order to bit-map an 875 line screen with a required resolution of 600 pixels, a memory of 800.times.600 or 480,000 bits is required for a black and white (monochromatic) display (800 lines out of 875 lines are active).
Using random access memory (RAM), the overhead time for writing and checking memory for each of several test patterns is undesirable. Alternatively, the use of programmable read only memory (PROM) requires the use of considerable integrated circuitry leading to an excessive amount of board space. In order to store four unique test patterns in PROM, the required memory size would be 96K 16 bit words (2 patterns each of 480.times.600 and 800.times.600). The present invention condenses this memory to less than 512 16 bit words, while adding minimal external circuitry.
Accordingly, it is the object of the present invention to provide an arrangement for displaying raster test patterns wherein all memory included in said arrangement contains valid display information and nothing for blank screen space. That is to say, the amount of memory is proportional to the complexity of the image displayed.